1. Field of the Invention
The present invention relates to a semiconductor device, and particularly, a semiconductor device including a Voltage Down Converter (VDC).
2. Description of the Background Art
External power supply potentials ext.Vdd supplied to semiconductor chips have been lowered in accordance with demands for reduction in power consumption of systems employing the chips. Although the external power supply potential ext.Vdd has been lowered, problems relating to reliability and others may practically occur if the external power supply potential is used as an operation power supply potential of transistors within the chip without converting it. In view of this, an internal power supply potential Vdd lower than external power supply potential ext.Vdd is generally generated within the chip for using it as the operation power supply potential of transistors.
FIG. 12 is a block diagram showing a structure of a synchronous dynamic random access memory (SDRAM) 501, which is an example of a conventional semiconductor chip.
Referring to FIG. 12, SDRAM 501 includes four banks, which have a total storage capacity of 256 megabits and can operate independently of each other. In SDRAM 501, read/write operations are performed in synchronization with a clock signal CLK which is externally supplied thereto. For performing an intended operation, a command determined by a combination of control signals /RAS, /CAS and /WE is applied thereto. Also, SDRAM 501 is externally supplied with appropriate or necessary signals such as a control signal /CS instructing chip selection as well as a control signal CKE instructing whether clock signal CLK is to be taken into SDRAM 501 or not.
SDRAM 501 further includes a power supply potential generating circuit 510 which is externally supplied with an external power supply potential ext.Vdd, and issues an internal power supply potential Vdd after lowering the voltage. Power supply potential generating circuit 510 includes a VDC control circuit 532 which receives row-related bank activating signals from row decoders and word drivers 10#0-10#3 provided corresponding to the respective memory array banks, and issues signals ICL, ICM and ICS, a Vref generating circuit 534 which generates a reference potential Vref, and a voltage down converter (VDC) 536 which receives reference potential Vref, and issues power supply potential Vdd by lowering external power supply potential ext.Vdd to the same level as reference potential Vref at a response speed corresponding to signals ICL, ICM and ICS.
VDC control circuit 532 issues signals ICL, ICM and ICS based on the active state of the bank and the command. VDC 536 operates with a response speed controlled by signals ICL, ICM and ICS, and supplies a current from a node supplied with external power supply potential ext.Vdd to a node issuing internal power supply potential Vdd so that internal power supply potential Vdd may be equal to reference potential Vref.
FIG. 13 is a circuit diagram showing a structure of VDC 536 shown in FIG. 12.
Referring to FIG. 13, VDC 536 includes a shifter circuit 602 which receives reference potential Vref and internal power supply potential Vdd, and shifts the input level, a comparator 604 which receives signals REF and SIG issued from shifter circuit 602, and makes a comparison between them, and a driver 606 which operates in accordance with the output of comparator 604 to supply a current from the node supplied with external power supply potential ext.Vdd to the node issuing internal power supply potential Vdd.
Shifter circuit 602 includes an NOR circuit 612 which receives a signal ACT and a signal CKEI, a P-channel MOS transistor 618 which is connected between a node receiving external power supply potential ext.Vdd and a node N61, and receives on its gate the output of NOR circuit 612, an N-channel MOS transistor 620 which is connected between nodes N61 and N62, and receives reference potential Vref on its gate, an N-channel MOS transistor 622 which is connected between node N62 and a ground node, and has a gate connected to a node N63, an N-channel MOS transistor 624 which is connected between nodes N61 and N63, and receives internal power supply potential Vdd on its gate, and an N-channel MOS transistor 626 which has a gate and a drain connected to node N63, and also has a source connected to the ground node. A signal REF is issued from node N62 of shifter circuit 602, and a signal SIG is issued from node N63.
Comparator 604 includes a P-channel MOS transistor 628 which is connected between a node supplied with external power supply potential ext.Vdd and node N64, and has a gate connected to a node N65, an N-channel MOS transistor 630 which is connected between nodes N64 and N66, and has a gate receiving signal REF, a P-channel MOS transistor 632 which has a source coupled to external power supply potential ext.Vdd, and has a gate and a drain connected to a node N65, an N-channel MOS transistor 634 which is connected between nodes N65 and N66, and has a gate receiving signal SIG, and N-channel MOS transistors 636, 638 and 640 which are connected in parallel between node N66 and the ground node, and have gates receiving ICL, ICM and ICS, respectively.
Comparator 604 issues from its node N64 a signal DO for controlling a current supplied from the driver.
Driver 606 includes a P-channel MOS transistor 642 which is connected between a node supplied with external power supply potential ext.Vdd and a node issuing internal power supply potential Vdd, and has a gate receiving signal DO.
Typical operation specifications of the SDRAM are called "PC100", and the following description will be given by way of example on an SDRAM conforming the PC100.
FIG. 14 is an operation waveform diagram showing waveforms of external signals in the write operation of SDRAM 501.
Referring to FIG. 14, these waveforms show an operation in the case where each of a RAS-CAS delay time tRCD and a row precharge time tRP is equal to 3 cycles, and a burst length BL is 4.
At time t1 and therefore at a rising edge of clock signal CLK, the device is supplied with a command ACT[0] activating row-related portions in bank 0. The command is supplied together with a bank address, and a number inside square brackets following each command represents the bank address.
A combination of signals A0-A12 is applied as a row address X for selecting one word line WL, and at the same time, a combination of signals BA0 and BA1 is applied as a bank address which designates bank 0.
At time t4 after three cycles, a command WRITE[0] for performing writing on word line WL, which is already active, is supplied in response to the rising edge of clock signal CLK. At the same time, column address Y formed of a combination of signals A0-A9 is applied, and the bank address is also applied. Command WRITE is determined by the combination of control signals /CS, /RAS, /CAS and /WE. For four cycles from time t4 to time t7, write data D0-D3 are applied in accordance with a combination of externally applied signals DQ0-DQ15, and are written into the memory cells.
At time t8, a command PRE[0] for resetting word lines WL in active bank 0 is externally supplied to the device. Command PRE is applied as a combination of control signals /CS, /RAS, /CAS and /WE. For reliably writing the data into the memory cells, a time tWR must be kept between writing of last data D3 and subsequent input of command PRE[0]. In the foregoing manner, the data can be written into a specific bank.
When the same bank is to be accessed subsequently, a time equal to row precharge time tRP or more is required before starting the access.
When the operation shown in FIG. 14 is performed, a current consumption with internal power supply potential Vdd of the SDRAM varies with time.
FIG. 15 is a schematic waveform diagram showing changes in current consumption.
In one row cycle shown in FIG. 15, i.e., in the cycle during which commands ACT, WRITE and PRE are executed, a current consumption with power supply potential Vdd starts to increase rapidly upon input of each command. Since the SDRAM performs fast reading and writing, the peak value and average value of the current consumption are very large during the reading and writing.
The current consumption is small for a period from time t2 to time t3 and a period from time t4 and time t5, and in other words, for periods Trs1 and Trs2 from completion of predetermined operations to input of next commands. In general, each of periods indicated by Trs1 and Trs2 is call an "active standby period". The active standby state is such a state that the row-related portions are already active, the column-related operations can be performed, and nevertheless the current consumption can be suppressed while keeping such a state.
The standby state of the SDRAM during the foregoing active standby period is different from that of the SDRAM during a so-called standby period, for which none of the row-related portions is active. Current consumption Ias in the active standby state is larger than current consumption Iss in the standby state because the row related portions are active in the active standby state. These consumed current Ias and Iss include the through current in comparator 604, which becomes one of the most dominant factors in some case.
For handling variations in current consumption with power supply potential Vdd, and suppressing the through-current in comparator during standby state to reduce total value of standby current, it is necessary to devise the control of VDC generating power supply potential Vdd.
As already described with reference to FIG. 13, VDC 536 is formed of the comparator and the driver. The operation speed of the comparator increases or decreases in accordance with a through-current flowing through the comparator, and it is preferable that this through-current is small during the standby period and the active standby period. In accordance with the current consumed with the power supply, therefore, the value of this through-current is switched by changing signals ICL, ICM and ICS which are issued from VDC control circuit 532.
Description will now be given on signals ICL, ICM and ICS issued from VDC control circuit 532. In comparator 604 shown in FIG. 13, a value of through-current Ic is restricted by N-channel MOS transistors 636, 638 and 640. Signal ICL is activated when the consumption of power supply current is large, and therefore increases the value of through-current. Signal ICM is active when the row-related circuits are active, and N-channel MOS transistor 638 determines the value of standby current during the active standby period. Signal ICS is active during the standby period, and N-channel MOS transistor 640 determines through-current Ic during standby.
In FIG. 15, therefore, signal ICS attains H-level, and signals ICL and ICM attain L-level during the standby periods before time t1 and after time t6.
When the current consumption value is large during periods between times t1 and t2, t3 and t4, and t5 and t6, both signals ICL and ICM are set to H-level, and through-current Ic goes to the maximum value.
During the active standby periods, e.g., between times t2 and t3, and t4 and t5, signal ICM is set to H-level, and signals ICL and ICS are set to L-level. In this state, the through-current slightly exceeds the through-current during the standby period.
Referring to FIG. 13 again, description will now be given on the operation of shifter circuit 602 and the relationship of control signals ICL, ICM and ICS with respect to through-current Ic.
In VDC 536 shown in FIG. 13, comparator 604 is not configured to receive reference potential Vref and internal power supply potential Vdd. Comparator 604 receives signals SIG and REF, which are the outputs of shifter circuit 602. Shifter circuit 602 receives reference potential Vref and internal power supply potential Vdd, and changes the levels thereof for issuing signals SIG and REF. The levels of signals SIG and REF can be approximately expressed by the following formulas: EQU SIG=(1/2).times.Vdd (1) EQU REF=Vref-(1/2).times.Vdd (2)
In these formulas, it is assumed that all the transistors forming the shifter circuit has equal sizes, and the substrate bias effect can be ignored. As can be seen from the formulas (1) and (2), the level conversion of signals SIG and REF is stably performed without an influence by external power supply potential ext.Vdd and process variations, and signals SIG and REF change in opposite direction with respect to each other.
Signals SIG and REF changes around centers which are approximately defined by half the levels of reference potential Vref and internal power supply potential Vdd, respectively. Therefore, N-channel MOS transistors 634 and 630 in the comparator receiving these signals can operate in saturated regions even if a potential Vc on a node N66 is close to the ground potential.
Since potential Vc on node N66 determines the lower limit of the amplitude of output signal DO of comparator 604, this lower limit can be relatively reduced by providing shifter circuit 602.
If this lower limit can be lowered, gate-source potential Vgs of P-channel MOS transistor 642 in driver 606 can be increased so that driver 606 can be effectively used. In other words, a voltage down converter having a sufficient current supply capacity can be achieved even if the transistor size of P-channel MOS transistor 642 is relatively small.
Additionally, since the comparator input acts in opposite direction, the response of signal DO can be advantageously high. Further, the transistor size in the driver can be reduced, the response does not lower even when through-current Ic of comparator 604 is suppressed. Since the transistors forming shifter circuit 602 have small sizes, it is possible to ignore increase in layout area caused by the shifter circuit.
As already described, the through-current is switched among three N-channel MOS transistors 636, 638 and 640 receiving respective signals ICL, ICM and ICS for making the setting to reduce through-current Ic of comparator 604 during standby. Assuming that N-channel MOS transistors 636, 638 and 640 have constants .beta. of values .beta.636, .beta.638 and .beta.640, respectively, there is a relationship of (.beta.636&gt;.beta.638&gt;.beta.640). Constant .beta. can be expressed by the following formula: EQU .beta.=(W/L).times..mu..times.C.sub.OX (3)
where W is a channel width of the transistor, L is a channel length of transistor, .mu. is an average surface mobility and C.sub.OX is a gate capacity per unit area.
In general, when the VDC including the shifter circuit is operating, through-current Ic of the comparator and through-current Is of the shifter circuit form a stationary current consumption of the VDC.
It is assumed that each of N-channel MOS transistors 630 and 634 has a constant .beta. of a value of .beta.c, and each of N-channel MOS transistors 620 and 624 has a constant .beta. of a value of .beta.s. When it can be considered that potential Vc is substantially equal to the ground voltage, Vgs of each of N-channel MOS transistors 630 and 634 is approximately equal to Vgs of each of N-channel MOS transistors 620 and 624. Therefore, a relationship expressed by the following formula is established between through-currents Ic and Is in VDC 536 shown in FIG. 13. EQU Ic=(.beta.c/.beta.s).times.Is (4)
Through-current Is is determined to be smaller than through-current Ic. However, excessively small through-current Is increases a delay time in the shifter circuit, i.e., the time required for charging/discharging the gate capacity of N-channel MOS transistor 630 when internal power supply potential Vdd changes. Therefore, .beta.c/.beta.s is set to about 10 at most.
It can be considered that through-current Ic determined by the formula (4) corresponds to the state where both signals ICL and ICM in FIG. 13 are at H-level. In this case, the current consumption in VDC is determined primarily by through-current Ic of the comparator, and through-current Is of the shifter circuit can be ignored.
In the case other than the above, through-current Ic of comparator 604 is restricted, and is smaller than that in the foregoing case. For example, when clock enable signal CKE is deactivated, portions such as a clock buffer consuming a large amount of power supply current are deactivated so that the whole consumption of the power supply current becomes very small.
In this case, only signal ICS is activated, and signals ICL and ICM are deactivated. Thereby, only N-channel MOS transistor 640 of the smallest size is turned on so that through-current Ic of the comparator is extremely suppressed. In this case, through-current Ic of the comparator can be nearly equal to through-current Is of the shifter circuit.
In the above active standby state, it is desired to reduce exhaustively the current consumption, and the through-current in VDC forms one of unignorable factors. However, through-current Is of the shifter circuit which is similar in magnitude to through-current Ic of the comparator is unavoidably present so that the whole current consumption of the chip cannot be suppressed to a large extent.